-*- Text -*-
   This is the file .../info/PCHard.nfo, which contains info
about the PC Hardware. It is intended for use by the MOOSE developpers not to
look into huge books sometimes full of uninteresting details (uninteresting to
the software developper), and none being complete enough so that you don't need
another books. It does not try to incorporate all the info about the PC
Hardware. Here is a list of sources:
- "Octek Jaguar 386 motherboard, user's manual"
- "The hardware of the PC XT and PC AT", by Henri Linen, 198?
- "The Serial Port, version 7", by Christian Blum, 1993, on usenet (newsgroups
 comp.{os,sys}.msdos.programmer, comp.sys.ibm.pc, c.s.i.p.hardware) (look for
 SERIALPC.ZIP on ftp sites).
- "The PC system programming BIBLE (Third Edition)" by Michael Tischer, 1993
- "Advanced MS-DOS" (for version 3.2) by Ray Duncan, 1986
- "8088 Assembler Language Programming: The IBM PC (second edition)", by
 David C. Willen and Jeffrey I. Krantz, 1983
- The sources from the Linux kernel and drivers.

File: PCHard.nfo		Node: Top	Up:(MOOSE.nfo)

   This file describes the functions provided by the BIOS, the standard PC
compatible ROM based software. It is far from complete, as I fill it only
when I need some information.

* Menu:

* Intro::			The PC motherboard.
* I/O map::			Summary of IO addresses.
* Interrupt map::		Summary of IRQs and NMI.
* DMA map::			Summary of DMA channels.
* CMOS RAM map::		Summary of Persistent RAM

PC Stuff (including AT enhancements):
* 8259A PIC::			Programming Interrupts
* 8253 Timer::			Using the 1.19 MHz (4.77MHz/4) Timer
* 8250 UART::			The serial port
* 8255 PPI::			Keyboard & other I/O
* 8237 DMAC::			Direct Memory Access
* NEC µPD::			The Floppy Disk controller

AT Stuff
* RTC ... ::			Real-Time Controller & Persistent CMOS memory

See also:
* The 80x86 Family of CPUs: (CPU_x86.nfo).

Node: I/O map	Up: Top

(All addresses are in Hex)
The ix86 family of processors allow adresses up to FFFF (16 bits)
The ISA bus allows addresses only up to 3FF (12 bits)
000-0FF is reserved for system board I/O, while 100-3FF are available for I/O.

* 000-01F:	DMA Controller 1, 8237
* 020-03F:	Programmable Interrupt Controller 1, Master, 8259
* 040-05F:	Timer, 8254
* 060-06F:	Keyboard Controller
* 070-07F:	Real Time Clock, NMI mask
* 080-09F:	DMA Page Register, 74LS612
* 0A0-0BF:	Programmable Interrupt Controller 2, Slave, 8259
* 0C0-0DF:	DMA Controller 2, 8237
* 0F0:		Clear Math Coprocessor Busy
* 0F1:		Reset Math Coprocessor
* 0F8-0FF:	Math Coprocessor Port
* 1F0-1F8:	Fixed Disk
* 200-207:	Game I/O
* 278-27F:	Parallel Printer Port 2
* 2F8-2FF:	Serial Port 2
* 300-31F:	Prototype Card
* 360-36F:	Reserved
* 378-37F:	Parallel Printer Port 1
* 380-38F:	SDLC, bisynchronous 2
* 3A0-3AF:	SDLC, bisynchronous 1
* 3B0-3BF:	Monochrome Display and Printer Adapter
* 3C0-3CF:	Reserved
* 3D0-3DF:	Color Graphics Monitor Adapter
* 3F0-3F7:	Disquette Controller
* 3F8-3FF:	Serial Port 1

Node: DMA map	Up: Top

DMA Channel
0:	Spare (8 bit transfer)
1:	SDLC (8 bit transfer)
2:	Floppy Disk (8 bit transfer)
3:	Spare (8 bit transfer)
4:	Cascade for DMA C 1
5:	Spare (16 bit transfer)
6:	Spare (16 bit transfer)
7:	Spare (16 bit transfer)

Node: Interrupt map	Up: Top

NMI:	Parity Error, or some VGA cards.

Master Interrupt Controller:
* IRQ 0: Timer
* IRQ 1: Keyboard
* IRQ 2: Cascade Interrupt
* IRQ 3: COM2, others
* IRQ 4: COM1, others
* IRQ 5: LPT2, others
* IRQ 6: free
* IRQ 7: LPT1, others

Slave Interrupt Controller
* IRQ 8: Real-Time Clock
* IRQ 9: (software redirected to IRQ 2)
* IRQ 10:
* IRQ 11:
* IRQ 12:
* IRQ 13: External Math Coprocessor
* IRQ 14: AT Hard Disk after access completion
* IRQ 15:

Node: CMOS RAM map	Up: Top

* 00-0D:	Real-Time Clock information
* 0E:		Diagnostic status byte
* 0F:		Shutdown status byte
* 10:		Diskette drive type A and B
* 11:		Reserved
* 12:		Diskette drive type C and D
* 13:		Reserved
* 14:		Equipment byte
* 15:		Low byte of base memory size
* 16:		High byte of base memory size
* 17:		Low byte of expansion memory size
* 18:		High byte of expansion memory size
* 19-2D:	Reserved
* 2E-2F:	2-byte CMOS checksum
* 30:		Low byte of expansion memory size
* 31:		High byte of expansion memory size
* 32:		Date century byte
* 33:		Information flags (set during power on)
* 34-3F:	Reserved

RTC info
byte:
* 0:	seconds
* 1:	second alarm
* 2:	minutes
* 3:	minute alarm
* 4:	hours
* 5:	hour alarm
* 6:	day of week
* 7:	date of month
* 8:	month
* 9:	year
* A:	Status Register A
* B:	Status Register B
* C:	Status Register C
* D:	Status Register D

Node: 8253 Timer	Up: Top


* The 8253 Chip::
* The 8253 on PC's::

Node: The 8253 Chip	Up: 8253 Timer

   It has three independent counters "timer channels" 0,1,2.
   Each can be programmed in one of six modes, referred as mode 0 to 5.
   Each channel has a two 16 bit "latch" and "counter" registers, and manage
two input signals "clock" and "gate" and one output signal "out".
   We set the counter value through the latch, and each time a pulse arrives
at clock, the counter is decremented by one. When zero is reached, a signal
is generated to out.

   The 8253 is programmed by outb'ing to is command register.

p.103 sams book.
   

Node: 8259A PIC		Up: Top

   PIC means Programmable Interrupt Controller

   This chip controls the IRQs on the PC board.
   XT's have one PIC, while AT's have two, one being used in "slave" mode.

* 8259 Programming::
* 8259 on PC's::

Node: 8259 Programming	Up: 8259A PIC



ICW sequences:		Initialization Control Word
==============
send ICW1 on port 0, remaining on port 1
ICW1 bit 0,0,0,1,LTIM,0,SNGL,IC4:
  LTIM: 0 by front, 1 by level
  SNGL: 1 iff single PIC (0 if slave/master); no ICW3 if SNGL
  IC4:  1 iff there is an ICW4
ICW2: INTR(7->3),0,0,0; INTR to generate
ICW3: for the master, bit n is set iff IRn is a slave.
      for a slave, number i such that slave is IRi on master
ICW4: 0,0,0,SNFM,BUF,M/S,AEOI,µPM
  SNFM: 1 iff nested interrupts (emboîtables)
  BUF:  1 in transmit mode
  M/S:  1=master, 0=slave
  AEOI: 1 iff automatic EOI
  µPM:  1 for 8086, 0 for 8080 or 8085

delay with a jmp $+2 on a 286

OCW sequences:		Operation Control Word
==============
OCW1 on port 1: mask of interrupts (0=enabled)
OCW2 on port 0: R,SL,EOI,0,0,L2,L1,L0
  R,SL,EOI
  0  0  1	non specific EOI
  0  1  1	specific EOI
  1  0  1	rotate non specific EOI
  1  0  0	rotate automatic EOI
  0  0  0	rotate automatic EOI
  1  1  1	rotate specific EOI
  1  1  0	code prioritaire
  0  1  0	nop
  L2,L1,L0:	level of interrupt processed iff SL=1
		(else IRQ of highest priority)
OCW3 on port 0: 0,-ESMM,SMM,0,1,P,RR,RIS
  P=1 iff polling
  RR,RIS
  0  0  don't read
  0  1  
  1  0  read IRR
  1  1  read ISR

Node: 8259 on PC's	Up: 8259A PIC

The master (only one on XTs) PIC is IO mapped to 020,021
The slave (from AT's on) PIC is IO mapped to 0A0,0A1

The BIOS maps IRQ 0-7 to INT 08-0F, and IRQ 8-F to INT 70-77:
BIOS Master ICW: 11,08,04,01
BIOS Slave ICW:  11,70,02,05

   PPI means Programmable Peripheral Interface

Node: DMA Page Register

DMA Channel	I/O Address (HEX)
0:		0087
1:		0083
2:		0081
3:		0082
5:		008B
6:		0089
7:		008A
Refresh:	008F
